1. Field of the Invention
This invention relates to the implementation of logic functions in an integrated circuit logic device, and more specifically to ensuring reliability of reading from and writing to a latch configuration data storage element.
2. Description of the Prior Art
Many complex integrated circuit chips require configuration information to be loaded after device reset or during normal operation to internally set up the proper state. To minimize the chip die area, this information is typically stored in latches that share common read/write lines ("bitlines"). A typical latch comprises two cross-coupled inverters (connected to form a loop), which holds a state until the state is overwritten in a write operation.
A prior art CMOS transistor latch circuit is shown in FIG. 1(a). To write data to a latch 5, write enable transistor 2 is turned on by an externally provided WRITE signal, enabling the inverting buffer 3 to provide the inverted DATAIN signal as a particular voltage (either Vcc or ground) to the bitline 1. Each inverter in FIG. 1(a) is (see FIG. 1(b)) conventionally a pair of CMOS transistors, one N-type "N" and the other P-type "P", with their gates connected to the inverter input and their drains commonly connected to the inverter output. Passgate 4 of FIG. 1(a) (shown as a single N-channel transistor, but which may alternatively be a CMOS transmission gate or a series of such structures) connects the latch 5 (including cross-coupled inverters 20, 22) to the bitline 1. Passgate 4 is turned on by a signal on line 8 in response to
(1) the ENABLE signal provided to transistors 12 and 13 as driven by inverters 16, 18 and PA1 (2) the address of this latch, which results in the gate terminals of all transistors 10 being held low.
In a complex integrated circuit chip, there are typically several latches 5 connected to each bitline 1. For each latch 5 there is a corresponding line 8 controlling a passgate 4. Transistors 10 in FIG. 1 are addressed differently for the different passgates 4 connected to the same bitline 1, and select which of several configuration latches shall connect to bitline 1.
When transistor 4 is first turned on, there is momentary logic contention if latch 5 is switching states, but the transistor characteristics of latch 5 are such that the output of inverter 20 is overpowered, and the value of the data stored in latch 5 becomes the logical state of bitline 1. The small numbers adjacent to or over each schematic symbol in FIG. 1(a) denote the size of the active area (channel region) of the transistors. The single number denotes width of the transistor, with the transistor length being the minimum allowed by the fabrication technology (currently about 1.0 .mu.m). Hence transistors 10 each have a channel width of 5 .mu.m; inverter 3 includes a P-type transistor of 30 .mu.m channel width and an N-type transistor of 20 .mu.m channel width.
To read data from latch 5, bitline 1 is floating (i.e. not being driven by any signal), when connecting passgate 4 is turned on as described above. This allows latch 5 to charge the bitline 1 voltage to the voltage which is the stored internal state (data) of latch 5. Read enable transistor 6 is then turned on (turning off P-type transistor 11) by the READ signal. Bitline 1 voltage is then inverted by inverting buffer 7 and read out as the DATAOUT signal.
Because of the capacitance of bitline 1, there is problematically a potential for "read disturb," whereby during a read operation, the latch data is lost when the latch 5 accidentally achieves the value of the floating bitline 1, which may have been left at high or low potential (different from that of latch 5) corresponding to the last voltage that was actively driven onto bitline 1.
To address the read disturb problem, a scheme for lowering the gate voltage of the passgate during a read operation while maintaining a full voltage during a write operation is disclosed in commonly assigned Hsieh, U.S. Pat. No. 4,820,937, [docket M-349] incorporated herein by reference. However, the circuit of Hsieh requires substantial complexity and hence expense.